
-- This is the template for Lab 3.  You should start with this;
-- it will make your life easier.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.all;

entity lab3 is
     port(
        key : in std_logic_vector(3 downto 0);  -- pushbutton switches
        sw : in std_logic_vector(17 downto 0);  -- slide switches
        ledg : out std_logic_vector(7 downto 0)); -- green LED's
end lab3 ;


architecture behavioural of lab3 is

    component datapath is
	     port(
   	    datapath_in : in std_logic_vector(7 downto 0);
		    mux1sel : in std_logic;
		    write : in std_logic;
		    writenum : in std_logic_vector(2 downto 0);
		    readnum : in std_logic_vector(2 downto 0);
		    loada : in std_logic;
		    loadb : in std_logic;
		    mux2sel : in std_logic;
		    funct : in std_logic_vector(1 downto 0);
		    loadc : in std_logic;
		    clk : in std_logic;
		    datapath_out : out std_logic_vector(7 downto 0));
    end component;
	 
signal appended_datapath_in : std_logic_vector(7 downto 0);

begin  
  appended_datapath_in <= "0000" & sw(17 downto 14);
	u0: datapath
		port map( 
	    	datapath_in => appended_datapath_in,
			mux1sel => sw(13),
			write => sw(12),
			writenum => sw(11 downto 9),
			readnum => sw(8 downto 6),
			loada => sw(5),
			loadb => sw(4),
			mux2sel => sw(3),
			funct => sw(2 downto 1),
			loadc => sw(0),
			clk => key(0),
			datapath_out => ledg);		

end behavioural;

